The present invention relates generally to improvements in delta-sigma modulator analog-to-digital converters, and particularly, to improvements in integrator circuits for delta-sigma analog-to-digital converters.
Various techniques of providing analog-to-digital conversion of signals are well known. One well-known oversampling analog-to-digital (A/D) conversion technique uses a delta-sigma modulator including one or more integrators, a comparator, and a digital-to-analog converter (DAC) in the feedback path. A low-pass decimation filter is used allowing the modulator to provide necessary filtering. Typically, it is desirable in the design of a delta-sigma modulator to reduce quantization noise, which may be achieved by providing a transfer function for the overall modulator that possesses high in-band gain and high out-of-band attenuation, thereby shaping the quantization noise spectrum advantageously. This is usually accomplished by use of higher order delta signal modulators, which include multiple integration stages. Higher order modulators become unstable and therefore oscillate for inputs that exceed certain bounds. Instability may also occur as a result of the modulator being powered up since, since powering up of operational amplifier integrators with arbitrary initial states may place the modulator in an unstable region of its state space. Therefore, higher order delta sigma modulators require circuitry for detecting instability and restoring or resetting the modulator loop back to a stable state.
One approach to correcting the instability found in higher order modulators (three or more integration stages) is to use state-variable clamping techniques. FIG. 2 shows an integration stage 18 of a modulator including an operational amplifier 20 having an integration capacitor 22 and a limiter 24 coupled between the non-inverting input and the output of the operational amplifier 20. A non-linear element, such as a limiter, coupled across the integrating capacitor 22 prevents large values from appearing at the integrator output. Typically, for a higher order modulator circuit, the non-linear elements are set to turn xe2x80x9cONxe2x80x9d at voltage levels of about 20-50% higher than the peak-to-peak integrator voltage swings. Examples of limiting schemes implemented in an integrator stage are shown in U.S. Pat. No. 5,977,895 by Murota et al., issued Nov. 2, 1999, entitled xe2x80x9cWAVEFORM SHAPING CIRCUIT FOR FUNCTION CIRCUIT AND HIGH ORDER DELTA SIGMA MODULATORxe2x80x9d, U.S. Pat. No. 6,064,326 by Krone et al., issued May 16, 2000, entitled xe2x80x9cANALOG-TO-DIGITAL CONVERSION OVERLOAD DETECTION AND SUPPRESSIONxe2x80x9d, and U.S. Pat. No. 5,012,244 by Wellard et al., issued Apr. 30, 1991, entitled xe2x80x9cDELTA-SIGMA MODULATOR WITH OSCILLATION DETECT AND RESET CIRCUITxe2x80x9d disclose known ways of detecting instability of a delta sigma modulator and restoring it to a stable state.
However, the closest prior art to the present invention is believed to be commonly assigned U.S. Pat. No. 6,362,763 by Wang, entitled METHOD AND APPARATUS FOR OSCILLATION RECOVERY IN A DELTA-SIGMA AID CONVERTER, issued Mar. 26, 2002.
FIGS. 1 and 2 herein indicate the circuit structure of the integrators included in the delta sigma modulator of the ""763 patent.
A problem with the delta sigma modulator shown in U.S. Pat. No. 6,362,763 is that its circuit topology is likely to result in unbalanced parasitic capacitances which produce errors due to the additional switch 70 that is coupled between the input notes of the differential amplifier 64. These parasitic-capacitance-errors are amplified by amplifier 64 and can substantially reduce the accuracy of the delta sigma modulator. Also, in some implementations, the switch 70 must be located a long distance on the semiconductor chip from the switch 72, which may necessitate use of different reset signals to control the two switches to ensure that they are simultaneously turned on and off to avoid errors at the sensitive (+) and (xe2x88x92) inputs of the amplifier 64.
Thus, there is an unmet need for an improved, inexpensive, stable delta sigma ADC of order greater than 1 that is more accurate than the one shown in a U.S. Pat. No. 6,362,763.
There also is an unmet need for a stable, more accurate delta sigma modulator in a delta sigma ADC of order greater than 1 which requires less chip area than the one shown in U.S. Pat. No. 6,362,763.
There also is an unmet need to avoid inaccuracy caused by unbalanced parasitic devices in the integrators of a delta sigma ADC of order greater than 1.
There also is an unmet need for a delta sigma modulator of order greater than 1 which avoids the need to generate an additional reset signal to prevent a delay between turn-off times of two integrator reset switches which are separated by a large distance on an integrated circuit chip.
It is an object of the present invention to provide an improved, stable, inexpensive delta sigma ADC of order greater than 1 that is more accurate than the one shown in a U.S. Pat. No. 6,362,763.
It is another object of the present invention to provide an improved, stable, inexpensive delta sigma ADC of order greater than 1 which requires less chip area than the one shown in U.S. Pat. No. 6,362,763.
It is another object of the present invention to provide a stable delta sigma modulator in a delta sigma ADC of order greater than 1 which avoids inaccuracy caused by unbalanced parasitic devices in the integrators of a delta sigma ADC of order greater than 1.
It is another object of the present invention to provide an improved delta sigma ADC of order greater than 1 which avoids the need to generate an additional reset signal to prevent a delay between turn-off times of two integrator reset switches which are separated by a large distance on an integrated circuit chip.
Briefly described, and in accordance with one embodiment thereof, the invention provide a delta sigma modulator circuit including circuitry for summing an input signal with a feedback signal representing signal conditions in a group of integrators to provide an input to a quantizer, circuitry for monitoring a signal at the quantizer output to produce a restore signal (RESETA) indicating an instability condition, and an integrator including a dual purpose switch (S3) that is operated together with first and second sampling switches to accomplish an input signal sampling operation and also is operated together with first and second charge transfer switches and an output reset switch to accomplish precise resetting of the integrator without being directly connected to the amplifier inputs.
In a described embodiment, a delta sigma modulator circuit that sums an analog input signal and a feedback signal to provide an input signal to a plurality of integrators (92, 94, 96) coupled sequentially between an output of a summing device and an input of a quantizer produces the feedback signal as an analog feedback signal representative of signal conditions in one or more of the integrators and monitors a signal at an output (88) of the quantizer and produces a restore signal (RESETA or RESET) in response to occurrence of an instability condition that is caused by a positive input overvoltage of the analog input signal (86) and is represented by the signal at the quantizer output (88). One or more of the integrators each includes first and second input terminals and first and second output terminals, first (S1A) and second (S1B) sampling switches, a first switch (S2C), first (C1) and second (C2) sampling capacitors, a second switch (S3), first (S2A) and second (S2B) charge transfer switches, an operational amplifier (64), first (66) and second (68) integrating capacitors, and a reset switch (S4). A first terminal of the first sampling switch (S1A) is coupled to the first input terminal and a first terminal of the second sampling switch (S1B) being coupled to the second input terminal. The second terminal of the first input sampling switch (S1A) is coupled to a first terminal of the first switch (S2C) and a first terminal of the first sampling capacitor (C1), a second terminal of the second input sampling switch (S1B) being coupled to a second terminal of the first switch (S2C) and a first terminal of the second sampling capacitor (C2). A second terminal of the first sampling capacitor (C1) is coupled to a first terminal of the second switch (S3) and a first terminal of the first charge transfer switch (S2A), a second terminal of the second sampling capacitor (C2) being coupled to a second terminal of the second switch (S3) and a first terminal of the second charge transfer switch (S2B). A second terminal of the first charge transfer switch (S2A) is coupled to a (+) input of the operational amplifier and a first terminal of the first integrating capacitor (66), a second terminal of the second charge transfer switch (S2B) being coupled to a (xe2x88x92) input of the operational amplifier and a first terminal of the second integrating capacitor (68). A second terminal of the first integrating capacitor (66) is coupled to a (xe2x88x92) output of the operational amplifier and a first terminal of the reset switch (S4), a second terminal of the second integrating capacitor (68) being coupled to a (+) output of the operational amplifier and a second terminal of the reset switch (S4). The first (S1A) and second (S1B) sampling switches are controlled by a first clock signal (xcfx861), the first switch (S2C) and the first and second charge transfer switches are controlled by a second clock signal (xcfx862), and the second switch (S3) is controlled by a derived clock signal (P1). The derived clock signal (P1) is generated in response to the first and second clock signals and the restore signal (RESETA). The reset switch is controlled by a reset signal (RESET) which is produced in response to the first and second clock signals and the restore signal (RESETA).
The derived clock signal (P1) is produced by performing a logical ORing function on the first clock signal, and the restore signal (RESETA) is produced by performing a logical ANDing function on the signal and the restore signal (RESETA), wherein the second switch (S3) and the reset switch (S4) are turned on or off precisely in response to corresponding changes in logical levels of the restore signal (RESETA).